When Hitachi Ltd. and IBM Corp. married their venerable storage divisions in January of this year to form Hitachi Global Storage Technology, the mutual attraction clearly was a desire to combine strengths and sustain a leadership position in the $22 billion disk drive market.

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来源:LM317 Electronics Components编辑:MaxStream (Digi International)时间:2021-06-14 03:43:17

When Hitachi Ltd. and IBM Corp. married their venerable storage divisions in January of this year to form Hitachi Global Storage Technology, the mutual attraction clearly was a desire to combine strengths and sustain a leadership position in the $22 billion disk drive market.

Size and Scalability An example implementation outlined above will have the following logic resources:

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This function consumes a relatively small amount of logic resources. The logic utilization can be further reduced by omitting the RNG from the design and relying on software or data derived random numbers instead. This will save the 820 logic cells required by the RNG and produce the minimal Diffie-Hellman Core as follows:

To give an idea of the relative size of this solution, the smallest low cost FPGAs contain about 3000 logic cells, with a current high-volume price of $4. Thus a hardware acceleration solution supporting both Diffie-Hellman and RSA, is available for about $1.

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Implementation Efficiency Standalone ASIC (or ASSP) implementations generally do not exist for Diffie-Hellman only implementations; instead they tend to be part of a more application specific device such as an IPSec security processor or SSL processor. Using the Diffie-Hellman only part of the chip may not be straight forward or cost effective, as the Diffie-Hellman engine may be closely tied to the overall functionality of the chip, and not available independently.

Generally these devices have an efficient implementation of the modular arithmetic function as well as the important random number generator. However, the modular arithmetic functionality may be tuned to particular protocols such as IPSec or SSL, which may not be suitable for a general-purpose solution.

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More commonly, general-purpose processors (GPPs), and sometimes digital signal processors (DSPs), are used to implement the modular exponentiation algorithms. There are many software libraries available, which can be targeted to a wide variety of platforms, allowing a programmer to implement any combination of key exchange and public key cryptography easily. Performance results for the processor approach can vary widely, dependant on the type of processor used, as well as the quality of the library. The major advantage to the processor approach is flexibility. There are two major disadvantages:

An alternative approach, as described in this article, is to use an FPGA with its general-purpose logic fabric partitioned into an embedded processor and an acceleration unit. For example, in the case of a 1024-bit exponent and modulus, it is possible to implement a radix-2 exponentiator that is 500 logic cells in size, and can achieve 32 key exchanges per second. This is for a very low cost, consumer product oriented device. Alternatively, using the higher performance FPGAs, which contains embedded 36×36 multipliers, a higher radix version of the modular exponentiation can be supported, that can achieve upto 640 key exchanges per second—again using only a small fraction of the resources of the device. Programmable logic compares favourably with both the performance and cost of ASSPs, but has the flexibility of processors; but more importantly, as the FPGA can be customized to any degree by the user, the design can be optimized for the application at hand.

Jitter is defined here as the difference in the time interval between a pair of consecutive CFrames belonging to a flow at the ingress and the interval between the same pair of CFrames at the egress. Jitter is specified in seconds and measures the difference in latency between two sequential CFrames belonging to the same flow. As with latency, the time is always measured from the start of the CFrame. The submetrics fabric jitter and total jitter measure, respectively, the ingress time interval at point 2 to the egress time interval at point 3, and the ingress time interval at point 1 to the egress time interval at point 3.

Data representation Performance metrics are presented as a graph, a table or both, as specified by the benchmark. Multiple performance metrics can be depicted in a single graph. Alternatively, graphs and tables can be combined. Graphs are for illustrative purposes only and do not necessarily reflect realistic fabric performance or a required benchmark.

The format of a standard performance metric graph is a plot of the average value of the performance metric vs. the experimental variable. In most cases, benchmarks are defined with only one changing experimental variable, such as the load; however, other experimental variables, such as packet size, are valid as well and can be plotted on the x axis.

There are two basic graph formats: full and abbreviated. The full format includes a standard-deviation bar along with the maximum and minimum values for each experimental variable value. It also includes the data in table form, attached to the graph. The abbreviated format includes only the average value for each experimental variable.

The full format is used when one performance metric is being presented, such as total latency, fabric latency or jitter performance. The accepted-vs.-offered bandwidth metric is inherently averaged and thus makes the abbreviated format much more suitable.

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