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来源:LM317 Electronics Components编辑:Dataman时间:2021-06-14 04:38:03

It's pretty stable now, but we're understaffed, as are most of us in the frequency-control market,” he said.

There has been much dire commentary from experts as to how Japan’s earthquake could, might, or may be very disruptive to our industry. It is true that the earthquake could, might, or may have been very disruptive to our industry. It was certainly a disruptive weekend and week if you work in supply chain management. But historically, these sorts of shocks to the supply chain have not been disruptive on an annual basis. Even this time, while there was a spike in flash prices on the Monday right after the quake, they were already moderating by the end of the week.

As big as the quake was, the primary source of problems for the industry is not the earthquake, nor even the tsunami. It was the low preparedness of Japan’s power industry. This includes poor regulatory oversight, political payoffs and choice of site location, making this a disaster waiting to happen.

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The biggest thing to learn from the table above is that recovery depends highly on how well prepared a company is in both the planning that went into siting and building the fab, as well as having ongoing safety processes in place. What made Taiwan’s Chi-Chi earthquake so bad was the fact that simple things like tying tools down and double containment of gases and chemicals were not in place. If the same earthquake were to happen today, Taiwan would come out far better. While the quake was severe, the vibration had largely dissipated by the time it hit the semiconductor production areas.

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While the Sendai earthquake was one of the worst in history and ranks first in big shakers for the semiconductor industry, the actual severity was limited because it was so far out to sea. Contrast the USGS shake map for Sendai against that for the Loma Prieta earthquake. In the areas where the closest fabs were, Loma Prieta was more severe. As for Toshiba’s flash fabs, they were way down past the green zone on the chart. This is why they sustained so little damage and recovered on the same day of the quake.

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Moreover, most of Japan’s semiconductor production was not affected by the Tsunami either. The biggest issues currently affecting Japan’s semiconductor production are the same as I wrote about last week: power and transportation. If a fab is subject to the 3-hour rolling blackouts, it can’t run. Moreover, Japan’s rail systems run on electricity and their scheduling systems didn’t incorporate plans for such an event.

As for Toshiba’s flash fabs, they have been able to get uninterrupted power, so this is not a problem there. This comes back to the point about planning for these disruptions: it’s always good to have your own source of power or at a minimum an exemption similar to what hospitals get where the power cannot be shut down. Another example is Globalfoundries' Dresden fab that was built with a co-generation plant. It paid for itself by selling power back into the grid during peak hours, just like a homeowner would do with solar panels. When a flood took out the local power plant, it went right on with no interruption.

Modeling of functionality, structure, and timing of aheterogeneous system at different levels of abstraction requires amix of features that cannot be found in any existing language. Inaddition, plain C++ system models are often inflexible due to thecentralized representation of concurrency and time—typicallya loop in the main program. To solve this, IMEC extended C++ withthe class library TIPSY (TImed Parallel SYstem modeling). TIPSYsupports a decentralized notion of concurrency and time in anexecutable model of an SoC.

A limitation in traditional languages and environments forsystem modeling is that they usually stress the specification offunctionality at a high level of abstraction without taking intoaccount architecture and timing. However, industrial experienceshows that architecture and timing are equally important at thebeginning of the design process. TIPSY encourages modeling ofarchitecture and timing in an initial abstract model and thensupports concurrent refinement of functionality, architecture, andtiming. This approach to system design is similar to solving ajigsaw puzzle: key pieces such as border pieces and pieces witheasily recognizable features are placed first with the remainingholes filled later.

TIPSY models concurrency by using non-preemptive multithreading.Threads or tasks can dynamically spawn and kill other tasks, andcan block (suspend) until resumed by another task or a timeout. Forefficiency reasons, each task has a local copy of the current timeand tasks synchronize their local times only when they communicate.Inter-task communication is based on shared data, for the practicalreason that it is the basic communication mechanism available in amulti-threading environment. Shared data allows an efficientimplementation of other communication primitives. Before accessingshared data, a task must synchronize its local copy of the currenttime with that of the other tasks. This ensures that shared dataaccesses are executed in correct time order.

TIPSY is the foundation for a rich set of C++ librariessupporting different modeling paradigms that can be easily combinedusing TIPSY's common notion of concurrency and time (Figure 5).Moreover, TIPSY supports the modeling of RTOS schedulers andpreemption in a very efficient way. This becomes increasinglyimportant, since an increasingly large part of a SoC designconsists of software running on an embedded processor under thecontrol of an RTOS.

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