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TMM-110-01-L-S-RA-005

来源:LM317 Electronics Components编辑:Acme Electric时间:2021-06-14 05:09:21

Saqib Jang is Principal at Margalla Communications, a Woodside,CA-based firm providing strategic and technical marketingservices to the storage & networking markets.He has several years of experience as a successful storage networking marketing consultant and industry analyst, and over fifteen years of experience in the product planning, development, marketing, and business development of industry-leading storage networking products.Mr. Jang holds a B.S. degree in Electrical Engineering from Massachusetts Institute of Technology (MIT) and an M.B.A. in Marketing from the Wharton School, University of Pennsylvania. He can be reached at saqibj@margallacomm.com

When two die are stacked, the new stack is often validated and tested again before the next phase in the fabrication process, which may involve adding another die to the stack. Clearly, test re-use and portability from one phase to the next will be essential if costs and yield loss are to remain in check.     Formulating a strategy for validating and testing a multi-die 3D device will require addressing a number of issues involving the three Ws: when, where and what. (The fourth W, why validate and test, is fairly self-evident.)

When are tests performed?

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As alluded to, tests will need to be run on individual bare die as well as incomplete and complete stacks of multiple die. Uncovering a fault or failure before another die is attached to a stack can allow for repair work that might otherwise be impossible when the 3D stack is completed and physical access to one of the inner die is impossible.

Correctly timing when an incomplete stack is discarded because it is beyond repair will reduce costs significantly. For example, if a two-die stack can be discarded before three more die are stacked on top of it, or if wafer-on-wafer stacking can match failing die patterns, the manufacturer is able to recoup significant cost in terms of time and material that might otherwise have been lost.

Where on the device are tests performed?  

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The upper and inner die in a stack will have no external pins or test pads that might provide access to probes for test purposes. Through-silicon vias (TSV) might be appropriated for test but the test strategy must take into consideration the bandwidth required to apply and run test vectors in a reasonable period of time.

Vectors that require too much time to be delivered from external automatic test equipment (ATE), and then applied and run on the chip will only drive up the cost of the device since the significant portion of test cost is test time. Of course, chip designers will want to minimize on-chip resources dedicated to validation and test; so, one of the first tradeoffs in developing a test strategy for a 3D device will probably involve test time vs. on-chip resources. Another ‘where’ question involves where the TSVs should be placed to facilitate efficient test (and, of course, how many TSVs are needed).

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What is the goal of test?

To start with, testing might be intended to validate the design and fabrication of each die so the eventual stack will be composed of known-good-die. Following this phase of die design and  manufacturing verification, the goal of test could expand into ensuring that the manufacturing processes related to stacking multiple die, such as back-grinding and laser drilling, have not broken anything in a stack of known-good-die. And then, if TSVs are being used for test, the operation of the test TSVs must be validated before test vectors can be run on them. On top of all this, tests could be conducted to evaluate and investigate new defect and fault models that might only arise in a stacked 3D device, such as vertical connectivity, thermal hot spots, voltage di/dt sensitivity, noise immunity and other potential interactions.

Figure 2 shows the effects of the TX SAW removal on a 3G mobile handset PCB.  In this example, the CMOS 3G PA is pin-compatible with the previously used GaAs PA which simplifies the implementation.  By moving to the CMOS 3G PA, designers could eliminate a TX SAW filter plus four additional components that were needed for matching around the TX SAW.  In this sample implementation, only the TX SAW filter, 3G PA, and matching components were changed.

In the Javelin design, the Bandpass PA architecture enables the removal of the TX SAW filter.  As the RF signal from the XCVR/BB passes through the PA, the unwanted out-of-band noise produced by the transceiver is filtered out by high performance analog circuitry integrated in the CMOS 3G PA die.  Furthermore, the thermal noise produced at the PA output is greatly reduced beyond the level of a conventional GaAs PA.  The resulting signal at the output is spectrally very clean, helping to ensure the best receiver sensitivity and producing minimal interference to other radios in the system.  Figure 3 shows the wideband gain response of the Bandpass PA architecture, demonstrating the integrated TX filtering capability.  Analysis reveals that this architecture provides about 15 dB of rejection in the 3G receiver band, and about 35 dB of rejection in the GPS band.

Figure 3: Javelin’s Bandpass PA” architecture.

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