Figure 3: Typical charge pump LED driver.

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来源:LM317 Electronics Components编辑:MtronPTI时间:2021-06-15 15:02:37

Figure 3: Typical charge pump LED driver.

One solution is to analyze the digital bits from the ADC directly. The ultimate solution for DigRF testing and characterization, the Agilent RDX platform provides a single test environment that helps you validate DigRF v4 protocols under real world conditions. With powerful emulation software and protocol-specific hardware test cards, you can quickly explore a broad range of test cases. The included protocol generation and analysis software interoperates with the industry-leading Agilent Signal Studio software and 89600 VSA analysis software to enable RF physical domain stimulus and analysis across an RF-IC chip.

The software allows you to analyze ADC performance by making traditional RF measurements directly on digital data, and it provides numerical error vector magnitude (EVM) performance measurements for verification along with detailed graphical information that can be used during product development to isolate the source of signal impairments.


The base station receiver faces many of the same MIMO challenges that the UE receiver faces, but in addition has to simultaneously receive data from multiple users. From the point of view of MU-MIMO, each signal comes from a separate UE, therefore each signal has a completely independent channel, somewhat different power levels, and different timing. These characteristics can be emulated using the Agilent N5106A MIMO receiver tester (PXB) in conjunction with RF signal generators.

In normal operation the receiver will have to deal with a complex and continuously changing channel, but using a fading channel to emulate these conditions means that tests will not be repeatable. A fading channel built from simple phase and timing differences between paths provides a deterministic signal that can be designed to verify the receiver’s performance limits. Adding noise to such a channel can readily create a test signal in which some subcarriers are more difficult to demodulate than others.

When a fading channel is required, a configuration such as that shown in figure 3 provides multiple, independent, continuously faded paths with analog or digital outputs.


The plots shown in figure 4, generated by the MIMO receiver tester, show the demodulated signals from a single frame of an LTE signal. The channel was flat-faded (no frequency selectivity). The two constellations at the top of the figure show the two layers of the MIMO signal. It is clear that the constellation on the left is tighter, which would result in a lower bit error ratio (BER) in a real receiver.

In open-loop MIMO operation the UE sends channel quality information (CQI) data to the eNB. The layer with higher CQI sustains higher order modulation or less channel coding. In closed-loop MIMO operation the UE additionally sends PMI data, which enables the eNB to cross-couple the streams to equalize the performance of the two layers, as seen in the lower plots.


In LTE, the codebook index method is used to facilitate channel precoding, with a small number of codes used to minimize the system overhead in signaling. This means that the codebook index provides an approximation to the channel, implying some level of residual error. Testing receiver precoding performance requires the use of signals with a fixed phase relationship to ensure repeatable test conditions. An example test system configuration is shown in figure 5.

Today’s design techniques rely on system simulation to avoid costly hardware iterations and to speed up the overall design process. It is helpful if the results can be applied directly to hardware testing. Agilent offers design tools that, later in the design process, can be interfaced with test instrumentation to give a mixed hardware and simulation environment, so that engineers can perform functional tests on completed components and subsystems in a system context. Figure 6 shows a complete transmitter and receiver with a faded MIMO channel using Agilent SystemVue.

High bandwidth digital downconverters (DDCs) are critical components in many high-performance systems, including receivers of modulated communications, medical imaging devices, and low-level RF control hardware for scientific research.

Modern graphical programming tools and commercial, off-the-shelf hardware have progressed to the point that they can be used to implement high-performance designs with minimal FPGA-specific knowledge. A number of such high-level and graphical design tools exist, along with a variety of FPGA-based I/O hardware.

Digital downconverter theory Many signal processing applications require both the magnitude and phase of a signal. These signals are typically acquired with high-speed, high-resolution analog-to-digital converters (ADCs), yet their information content does not occupy the entire Nyquist bandwidth of the ADC.

In these cases, the sample rate can be reduced, but only after frequency shifting the band of interest down to DC. To preserve both the magnitude and phase of the signal, along with frequencies both above and below the center of the target band, separate components of the signal 90 degrees out of phase must be retained. These are often referred to as the real and imaginary, complex, or in-phase (I) and quadrature (Q) components.

DDCs convert a real, time domain signal into a complex one, centered a baseband. The process of frequency conversion is achieved by mixing – or multiplying – the input signal with a digital sinusoid at the center of the bandwidth of interest. This creates copies of the signal of interest centered around zero, and also at twice the sinusoid frequency.

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