Sunnyvale, Calif. — Maxim Integrated Products Inc. claims that using this four-channel video switch instead of using traditional integrated audio/video switching devices can save money.

The width of the OS tree is given by *NOS * /3

When the input bits are high the tree height of a Wallace tree is less than that of an OS tree. For most common DSP applications, the word length is not particularly long—for instance, 12 to 24 bits. In these cases, there is no direct advantage to using Wallace trees . The Wallace tree height is only one level lower compared to the OS tree .

Some basic building blocks can be identified in the trees (Figure 7 ): body, root, connector, and branch. These building blocks can be used to form the general structure of the OS tree. The general structure can be easily derived. Assume that we have a tree of height nOS = j+1. A body of height j-1, a connector and a branch can construct the body of height j. The connector is constructed by two CSAs. The three outputs from the connector appear as inputs to the root, which is constructed by a single CSA. The branch height j-2 is formed by j-2 CSAs on top of each other with proper interconnections. Using these properties, an OS tree of arbitrary tree height can be constructed in an iterative way.

Figure 7: Structure of an OS Tree (7-9 inputs)

An 8-bit OS tree, which is designed for implementing FFT, is shown in Figure 8 .

Underflow Detection/Overflow or Saturation in Fractional MultiplicationWhen two n-bit integers A&B are multiplied, the result is a 2n bit number. The final product value is always greater then or equal to the greatest number among A&B. In the final result, when the only n least significant number is retained, an overflow may occur. However, in two n-bit fractional numbers, the result is still a 2n bit number, but the magnitude of the resultant product is lower than the lowest number among the A&B. Hence there exists a possibility of underflow in fractional multiplication. Overflow in fractional multiplication occurs when the multiplication -1X-1 is performed.

In order to keep the word length constant as required in many applications, only the n most significant bits are retained out of 2n bits in fractional multiplication .

The method used to retain 'n' most significant bits is either truncation or rounding. In truncation, the n least significant bits are truncated to retain n most significant bits. In rounding, the n least significant bits are truncated and for the remaining result after truncation a value 0.00…1 is added so that the final value is the value nearest to the original value. Thus for fractional multiplication, the least 'n' significant bits are retained. If the truncated number is a positive fraction, then add 0.0…1 to the retained value if truncated bits does not contain all zeros. If the truncated number is a negative fraction, then no correction factor is added and just 'n' most significant bits are related as the final value. The hardware circuit for the above concept can be implemented using multiplexer and some logic circuits (Figure 9 ).

The 8-bit by 8-bit Adder was implemented in the Xilinx XCV-1000-5bg 560 FPGA. This FPGA has an 1000K-gate capacity. After place and route and back annotation, the resources utilized were 1% of the total available. The simulation result is shown in Figure 10 .

In the above equations:

W & L are the physical length and width of the deviceVgs is the gate to source voltageVt is the threshold voltageVDS is the drain to source voltageK' is a factor based on the oxide capacitance and mobilityCox is the oxide capacitance T is the temperatureT0 is the initial temperature for a known value of Vt n is a factor determined by the process and is approximately 1.5α is the temperature dependence factor and is approximately -2mV/C

For a linear current limiting circuit, the FET would be operated in its saturation region. Equation 2 applies in this case, which has two main components that are temperature dependent, k' and Vt. Equation 2 has been rewritten to show the negative temperature dependence of these two terms.

If the value of Vgs is large relative to the value of Vt , then the k' term dominates and ID reduces with temperature. This is the mode of operation that most power engineers understand. The on resistance increases with temperature. This is very true for the case of a FET being used as a power switch where the gate drive level is fixed by the driver and is considerably greater than the Vt level.

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