Each digital receiver card samples four analog IF receptor signals from the PAF. The card consists of three major sections: analog-to-digital converters, a Virtex-6 LX130T FPGA and 10-Gbps optical data transmission components. Sampling is performed using two dual-input 8-bit ADCs from the semiconductor company e2v, sampling at a rate of 768 Msamples/s and providing a total bandwidth of 384 MHz. The Xilinx FPGA receives data from the ADCs as four source-synchronous 384-MHz DDR data streams. IDELAYs on these data lines are calibrated using an ADC test pattern.

Whereas the target for an 1149.1 boundary-scan operation is a TAP port on a chip, 1500 operations are intended to be applied at the IP core boundary, and P1687 operations are intended for instruments embedded inside a silicon die. This allows silicon suppliers to provide test and/or debug vectors that relate to their own test instruments no matter the access method. P1687 automation tools will use the device’s ICL description to bring these vectors either to a die’s edge, to the edge of a multi-die 3D device, or to the edge of a board or system that includes the multi-die 3D device.

The immediate task of the 1838 working group will certainly be facilitated by the options available to it. Included among the resources that the working group will be able to draw on will be the years of experience and vast installed base of resources associated with IEEE 1149.1 boundary scan, as well as the influx of new innovation brought about by recently passed or soon-to-be-ratified standards like IEEE 1149.7 and IEEE P1687.

About the author:

In addition to being a chief technologist at ASSET InterTech, Al Crouch is the co-chairman of the IEEE P1687 IJTAG working group and an editor for the IEEE P1838 3D test working group. He is a senior member of the IEEE and has filed for more than 30 test-related patents. He currently holds 15 patents.

The term Gray code is typically used to refer to a binary sequence in which only a single bit changes value when transitioning between adjacent states.

In this, the second installment of our mini-series, we take a look at generating Gray codes and also Binary-to-Gray and Gray-to-Binary conversions.

Just to refresh our memories, in Part 1 we considered the concept of Gray codes in general; in Part 3 we will ponder the generation of sub-2n Gray code count sequences; in Part 4 we will consider the generation of sub-2n sequences with consecutive values; and in Part 5 we will take a leap into the unknown to wrestle with the concept of n-ary” (non-Boolean) Gray codes.

Generating a Gray code Before we start, let's briefly remind ourselves as to the difference between a standard binary count and one of the many possible Gray code equivalents as illustrated in Figure 2-1 (we'll use 4-bit sequences for the purpose of these examples).

Commencing with a state of all zeros, a Gray code can be generated by always changing the least significant bit that results in a new state. An alternative method which may be easier to remember and use is as follows:

About the author:

In addition to being a chief technologist at ASSET InterTech, Al Crouch is the co-chairman of the IEEE P1687 IJTAG working group and an editor for the IEEE P1838 3D test working group. He is a senior member of the IEEE and has filed for more than 30 test-related patents. He currently holds 15 patents.

The term Gray code is typically used to refer to a binary sequence in which only a single bit changes value when transitioning between adjacent states.

In this, the second installment of our mini-series, we take a look at generating Gray codes and also Binary-to-Gray and Gray-to-Binary conversions.

Just to refresh our memories, in Part 1 we considered the concept of Gray codes in general; in Part 3 we will ponder the generation of sub-2n Gray code count sequences; in Part 4 we will consider the generation of sub-2n sequences with consecutive values; and in Part 5 we will take a leap into the unknown to wrestle with the concept of n-ary” (non-Boolean) Gray codes.

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