San Jose–June 14, 1998–Phoenix Technologies, Ltd. (San Jose) announced that it has signed an agreement with Sicore Systems, Inc. (Campbell, Calif.), who will provide design services for Phoenix's Virtual Chips line of synthesizable interconnect cores.

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ALF40C102EL350_Datasheet PDF

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San Jose–June 14, 1998–Phoenix Technologies, Ltd. (San Jose) announced that it has signed an agreement with Sicore Systems, Inc. (Campbell, Calif.), who will provide design services for Phoenix's Virtual Chips line of synthesizable interconnect cores.

Under the terms of the agreement, FMI will outsource the complete development of proprietary I/O library cells for their 0.25-m semiconductor process to Duet Technologies. The amount of the contract was not specified.

Duet will be responsible for the development and validation of specific I/O cells targeting Fujitsu's 0.25-m process including cell circuit design, physical layout, and verification, as well as documentation and release of the cells to FMI. The I/Os will also be crafted and optimized to work in both pad-limited and core-limited designs as well as in designs that mix 2.5-V and 3.3-V power supplies.

ALF40C102EL350_Datasheet PDF

Duet Technologies, Inc. 2833 Junction Ave.San Jose, CA 95134(408) 432-9200Fax: (408) 432-0907www.duettech.com

Fujitsu Microelectronics, Inc.San Jose, CA(800) 866-8608www.fujitsumicro.com

ALF40C102EL350_Datasheet PDF

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Los Gatos, Calif.–June 15, 1998–Open Verilog International (OVI; Los Gatos), an EDA industry organization, announced that the Verilog HDL synthesis interoperability standard was approved as an OVI standard.

ALF40C102EL350_Datasheet PDF

The Verilog synthesis interoperability standard benefits the electronicindustry by helping to insure consistent results across a broad spectrum ofapplications when designers reuse designs and intellectual property fromother sources. It provides a way to exchange and protect intellectualproperty.

The standard enables design reuse at the RTL and behavioral level byproviding a format for transferring designs and intellectual property amongdifferent EDA tools, so that they can operate on a design in a consistentand predictable manner.

XaQti Corp.1630 Oakland Road, Building A214San Jose, CA 95131(408) 487-0800Fax: (408) 487-0801www.xaqti.com

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San Jose–June 2, 1998–Atmel Corp. (San Jose) announcedit has licensed Palmchip Corp.'s (San Jose) Coreframe on-chip busarchitecture for its high-performance ASIC devices. This relationship willenable Atmel to accelerate the design of new system-on-a-chip integratedcircuits (ICs) and provide its ASIC customers withsystem-on-a-chip integration technology. Atmel's first implementation of theCoreframe IP will be in a cellular baseband application.

Coreframe is an on-chip interconnect architecture that allowssilicon functional blocks to be combined in asynthesis-friendly environment. It is optimized for use with the logicsynthesis and design verification tools available today from EDA software vendors. That enables designers to focus on their coredesign competencies while implementing Coreframe's plug-and-play architecture,thereby reducing system-on-a-chip design and verification time.

Atmel will offer Coreframe to its rapidly expanding ASIC customer base andalso use it internally for the development of new application-specificstandard products (ASSPs). The first applications to benefitwill be the mobile communications and digital imaging markets, whereability to handle high-bandwidth data streams is crucial.

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