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来源:LM317 Electronics Components编辑:APEX时间:2021-06-14 04:16:16

We will tackle the low-hanging fruit first. Do the easier things. We'd like to take the tester attributes and place those in the design environment. Today, we do that very generically. We now aim to get more specific information,” said Hsu.

As well as building closer links for research into linking design more closely with test, Mick Tegethoff, EDA and DFT marketing manager for Agilent, said: We create a critical mass to drive standards.”

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Hsu illustrated once case where closer integration could pay off at the DFT level. He described a situation where a Synopsys customer initially used scan-based test throughout a design but got poor results. By mixing the scan tests with other approaches, the overall coverage was greatly improved.

It took them a lot of iterations. If we can embed those tradeoffs and constraints in our tools, it could put an end to those iterations,” said Hsu.

Tegethoff said new approaches could let existing platforms cut the cost of handling analogue tests on SoC designs.

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At the wafer sort stage, if you can pick a min, or a max or a nominal test instead of doing all of them, you can save a lot of time.”

He said there is scope for tools that can help designers work out which test would work best for different types of analogue or mixed-signal block. The approach would at least isolate failed devices so that the others could go forward for more extensive testing.

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We want to go for just enough test,” said Tegethoff.

Logicvision has been busily signing up tester manufacturers for its own partners programme, but currently lack Agilent. Adding Advantest this week, Logicvision boasts LTX and Teradyne among its test hardware partners.

Fabrication implication

The long-term implication is that Mitsubishi has found another path to 50-nm (0.05-micron) CMOS fabrication, said Tsutsumi. At present we are not working at semiconductor device applications. However, I personally believe this can make very high aspect ratio trench etching. This is based on 50-nanometer pores. At the moment we are at 700 to 800 nanometers, but we have the possibility of going to 50 nanometers,” he said.

After a decade of research, conversion of electrical signals to light for high speed transmission at the die level, the module level, and the board level, is edging into production.  Suppliers say integration of photonics on silicon—with conventional CMOS technology—is what's needed to meet data center demands for next generation performance.     Optics is now a key bottleneck for the challenges of size, cost and power in the networking space, and CMOS photonics is the likely solution to those challenges,” suggests Mark Nowell, Cisco Systems senior director of engineering, CTO in the Shared Services and Transceiver Module Group, who will speak about the recent progress in the technology at SEMICON West in San Francisco in July. After years of R&D, it's now making the transition to commercial products.”

Making the optical modulators, multiplexers and detectors all in CMOS instead of assembling separate optical components greatly reduces size, cost and power usage. First applications have been active optical cables between server units and pluggable transceivers at the front panel, but moving the optical connections to the board level may be next. Analyst firm Yole Développement sees the silicon photonics market reaching some $215 million by 2017.

IBM takes a die-level monolithic approach with its 25-Gbps per channel WDM optical transceiver on single CMOS chip, announced in December, and now in qualification. The device integrates the optical modulator, photo detector and passive photonics features all in 90-nm CMOS.

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