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color code resistor value table

来源:LM317 Electronics Components编辑:Onion Corporation时间:2021-06-14 05:11:33

Dealing with DDR SDRAM All DDR memories use both edges of the memory clock to send and receive data. Normally, a DDR interface uses a clock that has a positive edge for every new data item on the bus. Such a clock actually runs twice as fast as is absolutely necessary, however, and thus wastes power. Power can be saved by using a clock running half as fast to switch the write data mux directly (as shown on the left side of Figure 2 ). Note that this scheme introduces a clock-as-data path.

color code resistor value table

Designers must also bear in mind that exceptions for a DDR interface's receiving registers must be specified. Although these registers are clocked at a single rate, data comes to them at a double rate. It is therefore imperative that exceptions are formulated that isolate the correct sending/receiving clock-edge pairs.

In Figure 2, the DDR clock labeled Clock becomes data through the DDR multiplex path. The DDR write data goes to the DDR receiving flip-flops as well as a monitoring flip-flop clocked by Clock2. It is desirable to false-path all paths from flip-flops clocked by Clock to all flip-flops clocked by Clock2. This step can normally be easily accomplished by setting a false path from clock object Clock to clock object Clock2. Unfortunately, this approach also false-paths the clock-as-data path for Clock to the flip-flop clocked by Clock2.

To handle this problem, the false-path scripts can be modified. First, a collection of all flip-flops clocked by Clock are generated, then the false path from this collection to the clock object Clock2 is declared:

color code resistor value table

set related_regs [all_registers –clock Clock]set pinname /CLK”foreach_in_collection reg_name $related_regs {set cellname [get_object_name $regname]set clkpin [concat $cellname$pinname ]set_false_path –from $clkpin –to [get_clocks Clock2]}

Timing paths in some off-the-shelf timing analysis tools are defined as originating on either an input port or flip-flop clock pin and terminating on either an output port or flip-flop data input pin. In the case of clock as data, the true source of the clock should be given, which is the pin on which the clock is declared.

color code resistor value table

Matching Data Send/Receive Paths Because the DDR data crosses a chip boundary, the data must be timed twice, first at the sub-chip level and later as part of the interface logic models (ILMs) sub-chip inside a top-level netlist. On the stand-alone sub-chip, the data paths end on output ports rather than flip-flops.

The dual role of Clock in the DDR transactions (see Figure 2 above) causes difficulties for STA. The Clock rising edge clocks both the high- and low-phase data into source registers (not shown in Figure 2). Clock also switches the mux that selects between the high- and low-phase data. Destination registers (when timing with an external hierarchical model) clock the DDR data in half a cycle later.

Test proponents have grown tired of saying this, but let's repeat: Design and test planning should be done together. Proper test planning is possible only through understanding of the process, the underlying design, and the available test tools. Test planners should perform cost analysis to gauge benefits and expenses involved before actually implementing a test strategy.

For example, a team could decide to use logic BIST exclusively and invests in a logic BIST tool, only to find out late in the game that their design is extremely random resistant. The perplexed team then has to turn around and design for full scan ATPG and invest in an ATPG tool. This will cause project delays, cost overruns, and reduced test coverage if it is too late to make some design changes.

Some key factors involved in test planning phase are types and capabilities of test hardware and software, test engineers, time to market, fab process and prevalent fault types. There is a pressing need for tools to critically analyze a given test strategy. A test investment based on thorough analysis of underlying design, proposed test techniques, and capabilities of available resources will set the stage for a low cost part for a horizontal IC manufacturer.

Phase 2, Implementation, is where the decisions most affect the risk of field returns, and hence the final selling price. It sets the wheels in motion to implement and verify the adopted test strategies, and consumes the most amounts of engineering resources. Sadly, it has the least amounts of tools available for a brilliant execution.

Yes, there are ATPG and BIST tools, but there is a tremendous amount of engineering required before using them, and after using them, to verify what they produce. For example, creating memory test models is a complex, laborious and mostly manual task. Some EDA vendors have partly automated test modeling, but such solutions are still complex and non-portable across different vendor tools. There is a need for bridging tools to create test models from RTL for all test tools.

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